High-nitrogen content metal resistor and method of forming same

ABSTRACT

A thin film metal resistor is provided that includes an in-situ formed metal nitride layer formed in a lower region of a metal nitride layer. The in-situ formed metal nitride layer, together with the overlying metal nitride layer, from a thin film metal resistor which has a nitrogen content that is greater than 60 atomic % nitrogen. The in-situ formed metal nitride layer is present on a nitrogen enriched dielectric surface layer. The presence of the in-situ formed metal nitride layer in the lower region of the metal nitride layer provides a two-component metal resistor having greater than 60 atomic % nitrogen therein.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.13/155,801, filed Jun. 8, 2011 the entire content and disclosure ofwhich is incorporated herein by reference.

BACKGROUND

The present disclosure relates to a semiconductor structure and a methodof forming the same. More particularly, the present disclosure providesa high-nitrogen content thin film metal resistor and a method of formingthe same.

A resistor is one of the most common electrical components, and is usedin almost every electrical device. In semiconductor device fabrication,it is well known to have thin film resistors embedded in theback-end-of-line (BEOL) structures of the chip through either adamascene approach or a subtractive etch method. BEOL thin filmresistors are generally preferred over other types of resistors becauseof lower parasitic capacitance. Conventional resistor materials andfabrication methods, however, present a number of challenges.

In one approach, the sheet resistivity of the various resistors formedover the entire wafer may vary and go beyond specifications due to poorprocess control. In an advanced manufacturing line, wafers out ofspecification are often scrapped for quality control, which isexpensive.

One material used for resistors is doped polysilicon. A problem withthis conventional resistor material is that it can only provide alimited resistance within a limited dimension, which presents problemsas further miniaturization of the device features continues. Resistivethin films such as chromium silicide (CrSi) and tantalum nitride (TaN)are also used as resistors in semiconductor devices. Prior art metalnitride resistors such as TaN are generally formed by physical vapordeposition and as such the nitrogen content within such resistors isless than 50 atomic percent. Manufacturing metal nitride resistorshaving a nitrogen content that is greater than 50 atomic % nitrogen isnot possible using prior art deposition techniques due to nitrogencontamination related problems which are inherently present in suchdeposition processes.

SUMMARY

The present disclosure provides a thin film metal resistor that has ahigh-nitrogen content associated therewith. In some embodiments, thethin film metal resistor of the present disclosure can be integratedwithin a back-end-of the line (BEOL) process.

The term “thin film” as used in conjugation with the metal resistor ofthe present disclosure denotes that the metal resistor has a physicalthickness of less than 500 nm. The term “high-nitrogen content” as alsoused in junction with the metal resistor of the present disclosuredenotes that the metal resistor has a nitrogen content that is greaterthan 60 atomic %. In contrast, prior art thin film metal resistors havea nitrogen content that is less than 50 atomic %. The increased nitrogencontent that is achieved by the thin film metal resistor of the presentdisclosure provides improved performance enhancement to the thin filmmetal resistor as compared to prior art thin film metal resistors. Byimproved “performance enhancement” it is meant that the metal resistorof the present disclosure provides higher electrical resistance ascompared to a prior art metal resistor having the same dimension.

The thin film metal resistor of the present disclosure includes anin-situ formed metal nitride layer that is formed in a lower region of adeposited metal nitride layer. The in-situ formed metal nitride layer,together with the overlying deposited metal nitride layer, from the thinfilm metal resistor of the present disclosure which has a nitrogencontent that is greater than 60 atomic % nitrogen. The in-situ formedmetal nitride layer is present on a nitrogen enriched dielectric surfacelayer. In accordance with the present disclosure, the in-situ formedmetal nitride layer is formed during and/or after formation of thedeposited metal nitride layer by reacting metal atoms from the depositedmetal nitride layer with nitrogen atoms present in the nitrogen enricheddielectric surface layer. The presence of the in-situ formed metalnitride layer in the lower region of the metal nitride layer provides atwo-component metal resistor having greater than 60 atomic % nitrogentherein.

In one embodiment of the present disclosure, a method of forming a thinfilm metal resistor having a high-nitrogen content (i.e., greater than60 atomic % nitrogen) is provided. The method of the present disclosureincludes forming a nitrogen enriched dielectric surface layer within anupper region of a dielectric material layer. After providing thenitrogen enriched dielectric surface layer, a metal nitride layer isformed thereon. During and/or after formation of the metal nitridelayer, another metal nitride layer forms in-situ in a lower region ofthe metal nitride layer. The another metal nitride layer is thus locatedbetween the nitrogen enriched dielectric surface layer and the overlyingdeposited metal nitride.

In some embodiments, a method is provided in which a resistor having ahigh-nitrogen content (i.e., greater than 60 atomic % nitrogen) isintegrated in a back-end-of the line integration process. In thisembodiment, the method includes providing a first dielectric materiallayer having at least one conductive material embedded therein. Adielectric capping layer is then formed atop the first dielectricmaterial layer and atop the at least one conductive material. A seconddielectric material layer is formed atop the dielectric capping layer,and thereafter a nitrogen enriched dielectric surface layer is formedwithin an upper region of the second dielectric material layer. Next, ametal nitride layer is formed atop the nitrogen enriched dielectricsurface layer. During and/or after the forming of the metal nitridelayer, another metal nitride layer forms in-situ in a lower region ofthe metal nitride layer. Another dielectric capping layer is then formedatop the metal nitride layer. The another dielectric capping layer, themetal nitride layer and the another metal nitride layer are thenpatterned to form a patterned material stack. A third dielectricmaterial layer having a plurality of conductive structures embeddedtherein is then formed atop the exposed nitrogen enriched dielectricsurface layer and the patterned material stack.

In another embodiment, the present disclosure relates to a semiconductorstructure that includes a resistor having a high-nitrogen content (i.e.,greater than 60 atomic % nitrogen) located on a nitrogen enricheddielectric surface layer. Specifically, the structure includes adielectric material layer having a nitrogen enriched dielectric surfacelayer located in an upper region thereof; a metal nitride layer locatedatop the nitrogen enriched dielectric surface layer, wherein the metalnitride layer is separated from the nitrogen enriched dielectric surfacelayer of the dielectric material layer by an in-situ formed metalnitride layer. In the disclosed structure, the metal nitride layer andthe in-situ formed metal nitride layer form a two-component metalresistor having a nitrogen content that is greater than 60 atomic %nitrogen.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a pictorial representation (through a cross sectional view)illustrating an initial structure including a first dielectric materiallayer having at least one conductive material embedded therein that canbe employed in one embodiment of the present disclosure.

FIG. 2 is a pictorial representation (through a cross sectional view)illustrating the initial structure of FIG. 1 after forming a dielectriccapping layer and a second dielectric material layer atop the initialstructure.

FIG. 3 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 2 after performing a surfacetreatment process that forms a nitrogen enriched dielectric surfacelayer in an upper portion of the second dielectric material layer.

FIG. 4 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 3 after forming a metal nitride layeron the nitrogen enriched dielectric surface layer.

FIG. 5 is a pictorial representation (through a cross second view)illustrating the structure of FIG. 4 in which another metal nitridelayer forms in-situ in a lower region of the metal nitride layer; theanother metal nitride layer that forms in-situ boasts the overallnitrogen content of the deposited nitride layer to greater than 60atomic % nitrogen.

FIG. 6 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 5 after forming another dielectriccapping layer atop the metal nitride layer.

FIG. 7 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 6 after patterning the anotherdielectric capping layer, the metal nitride layer and the another metalnitride layer.

FIG. 8 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 7 after further interconnectprocessing steps are performed.

FIGS. 9A and 9B are pictorial representations (through cross sectionalviews) depicting various high-nitrogen content metal resistors that canbe formed in the present disclosure. In each of the drawings, thehigh-nitrogen content metal resistor includes the metal nitride layerand the another metal nitride layer that forms in-situ in a lower regionof the metal nitride layer.

DETAILED DESCRIPTION

The present disclosure, which provides a high-nitrogen content metalresistor and a method of forming the same, will now be described ingreater detail by referring to the following discussion and drawingsthat accompany the present application. It is noted that the drawings ofthe present application are provided for illustrative purposes only and,as such, the drawings are not drawn to scale.

In the following description, numerous specific details are set forth,such as particular structures, components, materials, dimensions,processing steps and techniques, in order to provide a thoroughunderstanding of the various embodiments of the present disclosure.However, it will be appreciated by one of ordinary skill in the art thatthe various embodiments of the present disclosure may be practicedwithout these specific details. In other instances, well-knownstructures or processing steps have not been described in detail inorder to avoid obscuring the various embodiments of the presentdisclosure.

It will be understood that when an element as a layer, region orsubstrate is referred to as being “on” or “over” another element, it canbe directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

Reference is first made to FIG. 1 which illustrates an initial structure10 that can be employed in one embodiment of the present disclosure. Theinitial structure 10 includes a first dielectric material layer 12 thathas at least one conductive material 14 embedded therein.

The first dielectric material layer 12 of the initial structure 10 maybe located upon a substrate (not shown in the drawings of the presentapplication). The substrate, which is not shown, may comprise asemiconducting material, an insulating material, a conductive materialor any combination thereof. When the substrate is comprised of asemiconducting material, any material having semiconductor propertiessuch as, for example, Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InPand other III/V or II/VI compound semiconductors, may be used. Inaddition to these listed types of semiconducting materials, thesubstrate that is located beneath the first dielectric material layer 12can be a layered semiconductor such as, for example, Si/SiGe, Si/SiC,silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs).

When the substrate is an insulating material, the insulating materialcan be an organic insulator, an inorganic insulator or any combinationthereof including multilayers. When the substrate is a conductingmaterial, the substrate may include, for example, polySi, an elementalmetal, alloys of elemental metals, a metal silicide, a metal nitride orany combination thereof including multilayers. When the substratecomprises a semiconducting material, one or more semiconductor devicessuch as, for example, complementary metal oxide semiconductor (CMOS)devices can be fabricated thereon. When the substrate comprises acombination of an insulating material and a conductive material, thesubstrate may represent an underlying interconnect level of amultilayered interconnect structure.

The first dielectric material layer 12 that is employed in the presentdisclosure may comprise any interlevel or intralevel dielectricincluding inorganic dielectrics or organic dielectrics. In oneembodiment, the first dielectric material layer 12 may be non-porous. Inanother embodiment, the first dielectric material layer 12 may beporous. Some examples of suitable dielectrics that can be used as thefirst dielectric material layer 12 include, but are not limited to,SiO₂, silsesquioxanes, C doped oxides (i.e., organosilicates) thatinclude atoms of Si, C, O and H, thermosetting polyarylene ethers, ormultilayers thereof. The term “polyarylene” is used in this applicationto denote aryl moieties or inertly substituted aryl moieties which arelinked together by bonds, fused rings, or inert linking groups such as,for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like.

The first dielectric material layer 12 typically has a dielectricconstant that is about 4.0 or less, with a dielectric constant of about2.8 or less being more typical. All dielectric constants mentionedherein are relative to a vacuum, unless otherwise noted. Thesedielectrics generally have a lower parasitic cross talk as compared withdielectric materials that have a higher dielectric constant than 4.0.The thickness of the first dielectric material layer 12 may varydepending upon the type of dielectric material used as well as the exactnumber of dielectric layers within the first dielectric material layer12. When the first dielectric material layer 12 is an element of aninterconnect structure, the first dielectric material layer 12 may havea thickness from 50 nm to 1000 nm.

As stated above, the initial structure 10 also includes at least oneconductive material 14 embedded therein. As shown in FIG. 1, the atleast one conductive material 14 has an upper surface that is co-planarwith an upper surface of the first dielectric material layer 12. The atleast one conductive material 14 can be formed by first providing atleast one opening into the first dielectric material layer 12, and thenfilling the at least one opening with a conductive material.

The at least one opening that is formed into the first dielectricmaterial layer 12 can be formed utilizing lithography and etching. Thelithographic process includes forming a photoresist (not shown) atop thefirst dielectric material layer 12, exposing the photoresist to adesired pattern of radiation and developing the exposed photoresistutilizing a conventional resist developer. In some embodiments, a hardmask such as, for example, a layer of silicon oxide and/or siliconnitride, can be interposed between the photoresist and the firstdielectric material layer 12. The etching process includes a dry etchingprocess (such as, for example, reactive ion etching, ion beam etching,plasma etching or laser ablation), and/or a wet chemical etchingprocess. Typically, reactive ion etching is used in providing the atleast one opening into at least the first dielectric material layer 12.In some embodiments, the etching process includes a first patterntransfer step in which the pattern provided to the photoresist istransferred to the hard mask, the patterned photoresist is then removedby an ashing step, and thereafter, a second pattern transfer step isused to transfer the pattern from the patterned hard mask into theunderlying first dielectric material layer 12.

The depth of the at least one opening that is formed into the firstdielectric material layer 12 (measured from the upper surface of thefirst dielectric material layer 12 to the bottom wall of the at leastone opening) may vary. In some embodiments, the at least one opening mayextend entirely through the first dielectric material layer 12. In yetother embodiments, the at least one opening stops within the firstdielectric material layer 12 itself. In yet further embodiments,different depth openings can be formed into the first dielectricmaterial layer 12.

The at least one opening that is formed into the first dielectricmaterial layer 12 may be a via opening, a line opening, and/or acombined via/line opening. In one embodiment, and when a combinedvia/line opening is formed, a via opening can be formed first and then aline opening is formed atop and in communication with the via opening.In another embodiment, and when a combined via/line opening is formed, aline opening can be formed first and then a via opening is formed atopand in communication with the line opening. In FIG. 1, and by way of anexample, the at least one opening that houses the conductive material isshown as a line opening. When a via or line is formed, a singledamascene process (including the above mentioned lithography and etchingsteps) can be employed. When a combined via/line is formed a dualdamascene process (including at least one iteration of the abovementioned lithography and etching steps) can be employed.

Next, a diffusion barrier (not show) can be formed within the at leastone opening and atop the first dielectric material layer 12. Thediffusion barrier includes Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WNor any other material that can serve as a barrier to prevent aconductive material from diffusing there through. The thickness of thediffusion barrier may vary depending on the deposition process used aswell as the material employed. Typically, the diffusion barrier has athickness from 2 to 50 nm, with a thickness from 5 to 20 nm being moretypical. The diffusion barrier can be formed by a deposition processincluding, for example, chemical vapor deposition (CVD), plasma enhancedchemical vapor deposition (PECVD), atomic layer deposition (ALD),physical vapor deposition (PVD), sputtering, chemical solutiondeposition and plating.

In some embodiments, an optional plating seed layer (not specificallyshown) can be formed on the surface of the diffusion barrier. In casesin which the conductive material to be subsequently and directly formedon the diffusion barrier, the optional plating seed layer is not needed.The optional plating seed layer is employed to selectively promotesubsequent electroplating of a pre-selected conductive metal or metalalloy. The optional plating seed layer may comprise Cu, a Cu alloy, Ir,an Ir alloy, Ru, a Ru alloy (e.g., TaRu alloy) or any other suitablenoble metal or noble metal alloy having a low metal-platingoverpotential. Typically, Cu or a Cu alloy plating seed layer isemployed, when a Cu metal is to be subsequently formed within the atleast one opening. The thickness of the optional seed layer may varydepending on the material of the optional plating seed layer as well asthe technique used in forming the same. Typically, the optional platingseed layer has a thickness from 2 to 80 nm. The optional plating seedlayer can be formed by a conventional deposition process including, forexample, CVD, PECVD, ALD, and PVD.

A conductive material (which after deposition and planarization formsconductive material 14 in FIG. 1) is formed atop the first dielectricmaterial layer 12 and within the at least one opening. The conductivematerial may comprise polySi, SiGe, a conductive metal, an alloycomprising at least one conductive metal, a conductive metal silicide orcombinations thereof. In one embodiment, the conductive material is aconductive metal such as Cu, W or Al. In another embodiment, theconductive material is Cu or a Cu alloy (such as AlCu). The conductivematerial may be formed by a deposition process including chemical vapordeposition (CVD), plasma enhanced chemical vapor deposition (PECVD),sputtering, chemical solution deposition or plating that fills the atleast one opening from the bottom upwards. In one embodiment, abottom-up plating process is employed in forming the conductivematerial.

Following the deposition of the conductive material, a planarizationprocess such as, for example, chemical mechanical polishing (CMP) and/orgrinding, can be used to remove all material that is present outside theat least one opening forming at least conductive material 14 embeddedwithin the first dielectric material layer 12. The planarization stopson an upper surface of the first dielectric material layer 12 providingthe coplanar structure illustrated in FIG. 1. If a diffusion barrier andan optional plating seed layer are present, the planarization processwould provide a U-shaped diffusion barrier and a U-shaped plating seedlayer within the at least one opening. The U-shaped diffusion barrierand the U-shaped plating seed layer would be interposed between thefirst dielectric material layer 12 and the conductive material 14 thatis embedded therein. Also, the U-shaped diffusion barrier and theU-shaped plating seed layer would each have an upper surface that isco-planar with an upper surface of both the first dielectric materiallayer 12 and the conductive material 14.

Referring to FIG. 2, there is illustrated the initial structure 10 ofFIG. 1 after forming a dielectric capping layer 16 and a seconddielectric material layer 18 atop the initial structure 10, i.e., atopthe exposed upper surfaces of the first dielectric material layer 12 andthe at least one conductive material 14 that is embedded within thefirst dielectric material layer 12.

The dielectric capping layer 16 shown in FIG. 2 can include any suitabledielectric capping material such as, for example, SiC, Si₄NH₃, SiO₂, acarbon doped oxide, a nitrogen and hydrogen doped silicon carbideSiC(N,H) or multilayers thereof. The dielectric capping layer 16 can beformed utilizing a conventional deposition process such as, for example,chemical vapor deposition, plasma enhanced chemical vapor deposition,chemical solution deposition, evaporation, and atomic layer deposition.The thickness of the dielectric capping layer 16 may vary depending onthe technique used to form the same as well as the material make-up ofthe layer. Typically, the dielectric capping layer 16 has a thicknessfrom 15 to 100 nm, with a thickness from 25 to 45 nm being more typical.

The second dielectric material layer 18 shown in FIG. 2 may be comprisedof one of the dielectric materials mentioned above for the firstdielectric material layer 12. In one embodiment, the second dielectricmaterial layer 18 is comprised of a same dielectric material as thefirst dielectric material layer 12. In another embodiment, the seconddielectric material layer 18 is comprised of a different dielectricmaterial as the first dielectric material layer 12. The seconddielectric material layer 18 can be formed utilizing one of thedeposition processes mentioned above for forming the first dielectricmaterial layer 12, and the thickness of the second dielectric materiallayer 18 is within the range mentioned above for the first dielectricmaterial layer 12.

Referring to FIG. 3, there is illustrated the structure of FIG. 2 afterperforming a surface treatment, i.e., nitridation process, in which anitrogen enriched dielectric surface layer 20 is formed within anexposed upper surface of the second dielectric material layer 18. By“nitrogen enriched dielectric surface layer” it is meant, that theexposed upper surface of the second dielectric material layer 18 has ahigher nitrogen content therein after performing the nitridation processas compared to the originally deposited second dielectric material layer18. The nitrogen enriched dielectric surface layer 20 may also bereferred to as a nitrided surface.

As stated above, the nitrogen enriched dielectric surface layer 20 isformed by subjecting the structure shown in FIG. 2 to a nitridationprocess. In one embodiment, the nitridation process used in forming thenitrogen enriched dielectric surface layer 20 is a thermal nitridationprocess. When a thermal nitridation process is employed, no damage tothe second dielectric material layer 18 is observed. The thermalnitridation process that is employed in the present disclosure does notinclude an electrical bias higher than 200 W. In some embodiments, noelectrical bias is performed during the thermal nitridation process.

The thermal nitridation process employed in the present disclosure isperformed in any nitrogen-containing ambient, which is not in the formof a plasma. The nitrogen-containing ambients that can be employed inthe present disclosure include, but are not limited to, N₂, NH₃, NH₄,NO, and NH_(x) wherein x is between 0 and 1. Mixtures of theaforementioned nitrogen-containing ambients can also be employed in thepresent disclosure. In some embodiments, the nitrogen-containing ambientis used neat, i.e., non-diluted. In other embodiments, thenitrogen-containing ambient can be diluted with an inert gas such as,for example, He, Ne, Ar and mixtures thereof. In some embodiments, H₂can be used to dilute the nitrogen-containing ambient.

Notwithstanding whether the nitrogen-containing ambient is employed neator diluted, the content of nitrogen within the nitrogen-containingambient employed in the present disclosure is typically from 10% to100%, with a nitrogen content within the nitrogen-containing ambientfrom 50% to 80% being more typical.

In one embodiment, the thermal nitridation process employed in thepresent disclosure is performed at a temperature from 50° C. to 450° C.In another embodiment, the thermal nitridation process employed in thepresent disclosure is performed at a temperature from 100° C. to 300° C.

In addition to a thermal nitridation process, the formation of thenitrogen enriched dielectric surface layer 20 can include a plasmanitridation process. When a plasma nitridation process is employed, anelectrical bias of about 200 W or greater can be employed. The plasmanitridation process is performed by generating a plasma from one of thenitrogen-containing ambients that is mentioned above for the thermalnitridation process. In one embodiment, the plasma nitridation processemployed in the present disclosure is performed at a temperature from50° C. to 450° C. In another embodiment, the plasma nitridation processemployed in the present disclosure is performed at a temperature from100° C. to 300° C.

Notwithstanding the type of nitridation employed, the depth of thenitrogen enriched dielectric surface layer 20 may vary. Typically, thedepth of the nitrogen enriched dielectric surface layer 20, as measuredfrom the outer most exposed surface of the first dielectric materiallayer 18 inward, is from 0.5 nm to 20 nm, with a depth from 1 nm to 10nm being more typical.

Referring now to FIG. 4, there is illustrated the structure of FIG. 3after forming a metal nitride layer 24 on the nitrogen enricheddielectric surface layer 20. FIG. 5 illustrates the structure of FIG. 4after another metal nitride layer 22 forms in a lower region of themetal nitride layer 24 by the in-situ reaction of metal atoms from themetal nitride layer 24 with nitrogen atoms from the underlying nitrogenenriched dielectric surface layer 20. As shown, the another metalnitride layer 22 forms in a lower portion of the metal nitride layer 24(represented by the dotted lines in the drawings). As such, the anothermetal nitride layer 22 is positioned between the nitrogen enricheddielectric surface layer 20 and the metal nitride layer 24. Since theanother metal nitride layer 22 is formed in-situ, the another metalnitride layer 22 is composed of the same metal as that of metal nitridelayer 24.

In one embodiment of the present disclosure, the in-situ formation ofthe another metal nitride layer 22 occurs during the formation of themetal nitride layer 24. In another embodiment, the in-situ formation ofthe another metal nitride layer 22 occurs after complete formation ofthe metal nitride layer 24. In yet another embodiment, in-situ formationof the another metal nitride layer 22 occurs both during and afterforming the metal nitride layer 24. It is observed that the metalnitride layer 24 and the another metal nitride layer 22 that is formedin a lower region of the metal nitride layer 24 form the metal resistorof the present disclosure.

The metal nitride layer 24 that is formed in the present disclosureincludes, but is not limited to, TaN, TiN, RuN, CoN, WN and TaRuN. Inone embodiment, the metal nitride layer 24 is composed of TaN. The metalnitride layer 24 can be formed by a deposition process including, forexample, chemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), atomic layer deposition (ALD), physical vapordeposition (PVD), sputtering, chemical solution deposition and plating.Typically, the deposited metal nitride layer 24 that is formed has anitrogen content that is less than 50 atomic % nitrogen. However, afterthe another metal nitride layer 22 forms in-situ, the combination of themetal nitride layer 24 and the another metal nitride layer 22 provides ametal resistor that has a nitrogen content that is greater than 60atomic %. The metal nitride layer 24 that is formed typically has athickness from 2 nm to 50 nm, with a thickness from 5 nm to 20 nm beingmore typical. The another metal nitride layer 22 that is formed in-situtypically has a thickness from 0.5 nm to 20 nm, with a thickness from 1nm to 10 nm being more typical.

In some embodiments of the present disclosure, a bilayer resistorcontaining the another metal nitride layer 22 and the metal nitridelayer 24 is formed. The bilayer resistor has a distinct interfacebetween the another metal nitride layer 22 and the metal nitride layer24. This is shown in FIG. 9A. In another embodiment, and as shown inFIG. 9B, a gradient resistor is formed in which the content of nitrogenwithin the structure decreases upward from the nitrogen enriched surfacelayer 20 of the second dielectric material layer 18.

It is noted that in the various embodiments of the present disclosure,the nitrogen content within the nitrogen enriched dielectric surfacelayer 18 typically decreases after forming the in-situ metal nitridelayer 22 from its original value.

Referring now to FIG. 6, there is illustrated the structure of FIG. 5after forming another dielectric capping layer 26 atop the metal nitridelayer 24. The another dielectric capping layer 26 may include one of thematerials mentioned above for dielectric capping layer 16. In oneembodiment, the another dielectric capping layer 26 includes the samedielectric material as dielectric capping layer 16. In anotherembodiment, the another dielectric capping layer 26 includes a differentdielectric material as dielectric capping layer 16. The anotherdielectric capping layer 26 can be formed utilizing one of thetechniques mentioned above for forming dielectric capping layer 16.Also, the another dielectric capping layer 26 can have a thicknesswithin the range mentioned above for dielectric capping layer 16.

Referring now to FIG. 7, there is illustrated the structure of FIG. 6after patterning the another dielectric capping layer 26, the metalnitride layer 24 and the another metal nitride layer 22 into a patternedmaterial stack. The patterned material stack includes the high-nitrogencontent metal resistor of the present disclosure. The patterning of theanother dielectric capping layer 26, the metal nitride layer 24 and theanother metal nitride layer 22 can be achieved by lithography andetching. The etching step may include a single etch. Alternatively,multiple etching steps can be used in patterning the another dielectriccapping layer 26, the metal nitride layer 24 and the another metalnitride layer 22. As shown in the drawings, the patterned anotherdielectric capping layer 26′, the patterned metal nitride layer 24′ andthe patterned another metal nitride layer 22′ have sidewalls that arevertical coincident to each other. The etching step can stop atop anupper surface of the nitrogen enriched dielectric surface layer 20, orit can stop on an upper surface of the second dielectric material layer18. In the later embodiment, portions of the nitrogen enricheddielectric surface layer 20 that are not protected by the patternedmaterial stack can be removed.

Referring now to FIG. 8, there is illustrated the structure of FIG. 7after further interconnect processing steps are performed. The furtherinterconnect processing steps may include formation of a thirddielectric material layer 28 and metal structures 30 and 32. As shown,metal structures 30 extend to, and are in direct contact with, an uppersurface of the at least one conductive material 14 formed in the firstdielectric material layer 12, while metal structures 32 extend to, andare in direct contact with, an upper surface of the patterned metalnitride layer 24′. In one embodiment, and as shown, the metal structures32 are located an opposing ends of the patterned metal nitride layer24′.

The third dielectric material layer 28 may comprise one of thedielectric materials mentioned above for the first dielectric materiallayer 12. In one embodiment, the third dielectric material layer 28 maycomprise the same dielectric material as the first dielectric materiallayer 12. In another embodiment, the third dielectric material layer 28may comprise a different dielectric material as the first dielectricmaterial layer 12. The third dielectric material layer 28 can be formedutilizing one of the techniques mentioned above for the first dielectricmaterial layer 12. The thickness of the third dielectric material layer28 is also within the range mentioned above for the first dielectricmaterial layer 12. Typically, the thickness of the third dielectricmaterial layer 28 is greater than the thickness of the first dielectricmaterial layer 12.

The metal structures 30 and 32 can include one of the conductivematerials mentioned above for conductive material 14. In one embodiment,the metal structures 30 and 32 may comprise the same conductive materialas conductive material 14. In another embodiment, the metal structures30 and 32 may comprise a different conductive material as conductivematerial 14. The metal structures 30 and 32 can be formed utilizing thesame technique as mentioned above for forming the conductive material 14embedded in the first dielectric material 12. That is, lithography,etching and filling openings with a conductive material can be employed.In some embodiments, a diffusion barrier and a plating seed layer can beformed prior to filling the openings with the conductive material.Following the filling of the openings with at least the conductivematerial, a planarization process can be performed in order to form thestructure illustrated in FIG. 8.

While the present disclosure has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present disclosure. It is therefore intended that the presentdisclosure not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

What is claimed is:
 1. A metal resistor structure comprising: adielectric material layer having a nitrogen enriched dielectric surfacelayer located in an upper region thereof; and a metal nitride layerlocated atop said nitrogen enriched dielectric surface layer, whereinsaid metal nitride layer is separated from said nitrogen enricheddielectric surface layer of said dielectric material layer by an in-situformed metal nitride layer.
 2. The metal resistor structure of claim 1,wherein said metal nitride layer and said in-situ formed metal nitridelayer comprise a bilayer resistor with a distinct interface locatedtherebetween.
 3. The metal resistor structure of claim 1, wherein saidmetal nitride layer and said in-situ formed metal nitride layer providea resistor having a graded nitrogen content.
 4. The metal resistorstructure of claim 1, wherein said metal nitride layer and said in-situformed metal nitride layer provide a resistor having greater than 60atomic % nitrogen located therein.
 5. The metal resistor structure ofclaim 1, wherein said metal nitride layer and said in-situ formed metalnitride layer are components of a patterned resistor structure, andwherein another dielectric material layer is located on exposed portionsof said nitrogen enriched dielectric surface layer and said patternedresistor structure, and further wherein said another dielectric materialincludes a plurality of conductive structures embedded therein.
 6. Themetal resistor structure of claim 5, wherein a first conductivestructure of said plurality of conductive structures is direct contactwith one portion of said metal nitride layer, and wherein a secondconductive structure of said plurality of conductive structures isdirect contact with another portion of said metal nitride layer.
 7. Themetal resistor structure of claim 1, wherein said nitrogen enricheddielectric surface layer extends from 0.5 nm to 20 nm into saiddielectric material layer.
 8. The metal resistor of claim 1, whereinsaid metal nitride layer is selected from the group consisting of TaN,TiN, RuN, CoN, WN and TaRuN.
 9. The metal resistor of claim 1, whereinsaid metal nitride layer includes less than 50 atomic % nitrogen. 10.The metal resistor of claim 1, further comprising another dielectricmaterial layer located beneath said dielectric material layer havingsaid nitrogen enriched dielectric surface layer, wherein said anotherdielectric material layer comprises at least one conductive materialembedded therein.
 11. The metal resistor of claim 10, wherein said atleast one conductive material has an upper surface that is coplanar withan upper surface of said another dielectric material layer.
 12. Themetal resistor of claim 11, further comprising a dielectric cappinglayer located between said another dielectric material layer and saiddielectric material layer.
 13. The metal resistor of claim 12, whereinsaid dielectric capping layer is selected from the group consisting ofSiC, Si₄NH₃, SiO₂, a carbon doped oxide, and a nitrogen doped siliconcarbide.
 14. A semiconductor structure comprising: a first dielectricmaterial layer having at least one conductive material embedded therein;a first dielectric capping layer located on an upper surface of saidfirst dielectric material layer and partially on an upper surface ofsaid at least one conductive material; a metal resistor structurelocated on a portion of an upper surface of said first dielectriccapping layer, said metal resistor comprising: a second dielectricmaterial layer having a nitrogen enriched dielectric surface layerlocated in an upper region thereof; and a metal nitride layer locatedatop said nitrogen enriched dielectric surface layer, wherein said metalnitride layer is separated from said nitrogen enriched dielectricsurface layer of said dielectric material layer by an in-situ formedmetal nitride layer; and a second dielectric capping layer located on anupper surface of said a metal nitride layer.
 15. The semiconductorstructure of claim 14, wherein said second dielectric capping layer hasouter edges that are not vertically coincident to outer edges of saidmetal nitride layer and said in-situ formed metal nitride layer.
 16. Thesemiconductor structure of claim 15, further comprising a thirddielectric layer located atop and surrounding said metal resistorstructure.
 17. The semiconductor structure of claim 16, wherein saidthird dielectric layer includes a first metal structure contacting asurface of said at least one conductive material in said firstdielectric material layer, and a second metal structure contacting aportion of said metal nitride layer of said metal resistor structure.